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3 revisions	Sara Carlstead Brumfield at Sep 21, 2020 02:43 PM	Compared with
Sep 21, 2020 Sara Carlstead Brumfield Sep 20, 2020 trojana Mar 30, 2018 Stanford University Archives	15 2300 29 Sep 67 Checked timing on WRITE in 167 unity alternate 1's & 0' graf Some to be in specs. checked delay between SR-BR T0 and SR-BR T1. It is exactly 100ns. Run Time slizing Disk tester. No problems with reading or writing except one apparent care of an invalid sector address being transmitted The condition was inadvertently cleared before it could be investigated. ARR 0052 30 Sep 67 got hanging in TS DSK TST invalid secor Disk address reg: 3777654 Address sent by program was certainly less than 22777. ARR	15 2300 29 Sep 67 Checked timing on WRITE in 167 unity alternate 1's & 0' graf Some to be in specs. checked delay between SR-BR T0 and SR-BR T1. It is exactly 100ns. Run Time slizing Dick tester. No problems with reading or writing except one apparent care of an invalid sector address being transmitted The condition was inadvertently cleared before it could be investigated. ARR 0052 30 Sep 67 got hanging in TS DSK TST invalid secor Dick address reg: 3777654 Address sent by program was certainly less than 22777. ARR

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