15

1-11-67

CORE SA's Margins with High Speed Memory Checker Board

"0" Not Checked
"1" +10/-10
"2" +10/-10
"3" +9.5/-10

Back 1 B,C,D,E // Prog 16K CBD -9/10 // CORE 3
Back 1 L,M // Prog 16K CBD -10/+10 // CORE 3
Back 2 H,J,K,L // Prog 16K CBD -10/+10 //CORE 3
Back 6684 // Prog 16K CBD -2.8/+7.8 //CORE 3

In Core 3 current readings
IL131-IL133 [ant?] 4.5 ma // duration 640ns/1280ns
IL147-IL149 [ant?] 2.2 ma // duration 1380 - 1440 ns

2L // upper // write 1 [ant?] 250 ma duration 560 ns
2L // upper // write 2 [ant?] 250 ma duration 600 ns
2L // upper // write 3 [ant?] 250 ma duration 540 ns
2L // upper // write 4 [ant?] 259 ma duration 600 ns

2L Lower Read 1-4 250 ma 600 ns

Ran mechanical margins on all modules and connectors in CORE 3
Found 2 marginal [balun?] boards in [?] and 3 in 1K. Erasing the boards and working them in and out several times cured all of them. Core 3 is in good shape.

[SRC?]

1-11-67

CORE SA's Margins with High Speed Memory Checker Board

"0" "1" "2" "3"

Not +10 +10 +9.5
Checked -10 -10 -10

Back Prog
1 B,C,D,E 16K CBD -9
+10
1 L,M " -/+10 }Core 3
2 H,J,K,L " -/+10
6684 " -2.8/+7.8

In Core 3 current readings
[ant?] duration
IL131-IL133 4.5 ma 640ns/1280ns
IL147-IL149 2.2 ma 1380 - 1440 ns

[ant?] duration
2L upper WRITE 1 250 ma 560 ns
" 2 " 600 ns
" 3 " 540 ns
" 4 " 600 ns

2L Lower Read 1-4 250 ma 600 ns

Ran mechanical margins on all modules and connectors in CORE 3
Found 2 marginal [balun?] boards in [?] and 3 in 1K. Erasing the boards and working them in and out several times cured all of them. Core 3 is in good shape.

[(initials)?]